2016-09-05T00:03:10Z nyef whimpers.
2016-09-05T00:03:28Z nyef: This closure is using NARGS as a temporary for COMPUTE-CODE-FROM-FN.
2016-09-05T00:04:07Z nyef: Okay! Problem found. That's step one.
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2016-09-05T00:08:27Z nyef: Hrm.
2016-09-05T00:08:50Z nyef suspects that this is rather widespread, but not often obviously triggered.
2016-09-05T00:10:00Z nyef: Alpha considers NARGS to be a descriptor-reg.
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2016-09-05T00:10:31Z nyef: x86oids are special anyway.
2016-09-05T00:10:37Z nyef: Everything else seems to be vulnerable?
2016-09-05T00:10:59Z nyef: Please tell me that I'm missing something here?
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2016-09-05T00:26:18Z nyef: Please tell me that I'm missing something here?
2016-09-05T00:28:52Z nyef: Gah! ARM is vulnerable to a race condition here. )-:
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2016-09-05T00:48:49Z stassats: in compute-code-from-fn?
2016-09-05T00:50:27Z nyef: In the equivalent. The TEMP is a non-descriptor-reg, but it's used to hold descriptor data.
2016-09-05T00:51:54Z stassats: arm64 declares the temp but never uses it
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2016-09-05T01:06:07Z stassats: ok, i removed it from arm64
2016-09-05T01:06:33Z stassats: can do the rounds on arm, but not today
2016-09-05T01:06:47Z stassats: will have to make sure that the same temp is not used by anything else
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2016-09-05T01:13:40Z nyef: Ugh. Register pressure. I can't "just" make NARGS into a descriptor-reg, one of the descriptor-regs has to be come a non-descriptor-reg if I do that.
2016-09-05T01:14:03Z stassats: that's where?
2016-09-05T01:14:09Z nyef: ... And I forgot about updating the boxed-register list in sparc-lispregs.h. /-:
2016-09-05T01:14:40Z stassats: come to arm64 land, where i can blow a register and not even use it
2016-09-05T01:14:56Z nyef: eesh.
2016-09-05T01:15:01Z stassats: incidentally, i blame define-instruction on not reporting unused variables
2016-09-05T01:15:30Z nyef: Oddly enough, I'm suspecting that unused variables in instruction definitions are reported, but don't cause build failures.
2016-09-05T01:16:02Z stassats: i'm too afraid to touch the ball of mud that define-instruction is
2016-09-05T01:16:06Z stassats: it might bite back
2016-09-05T01:16:36Z nyef: That I can understand.
2016-09-05T01:17:02Z stassats: well, it doesn't report anything
2016-09-05T01:17:14Z stassats: (LET ((SB-ASSEM::HOOK (SB-ASSEM::SEGMENT-INST-HOOK SEGMENT))) (WHEN SB-ASSEM::HOOK (MULTIPLE-VALUE-CALL SB-ASSEM::HOOK SEGMENT #:VOP "XRELEASE2" ABC)))
2016-09-05T01:18:32Z nyef: Okay, sparc is offline for the night.
2016-09-05T01:18:48Z nyef: Possibly for a good chunk of tomorrow, as well.
2016-09-05T01:20:53Z stassats: now that i've touched define-instruction, it looks to expand into too much code
2016-09-05T01:23:08Z stassats: what is this postits thing?
2016-09-05T01:23:21Z nyef: Notes?
2016-09-05T01:23:35Z stassats:   ;; *** State used by the scheduler during instruction queueing.
2016-09-05T01:23:36Z stassats:   ;;
2016-09-05T01:23:36Z stassats:   ;; a list of postits. These are accumulated between instructions.
2016-09-05T01:23:40Z stassats: instruction queuing?
2016-09-05T01:25:26Z nyef: That'd be for the scheduling part of the assembler.
2016-09-05T01:26:11Z stassats: what's that? for emitting labels or something?
2016-09-05T01:26:53Z nyef: Don't remember.
2016-09-05T01:26:56Z nyef: Might be.
2016-09-05T01:27:05Z stassats: i smell dead code
2016-09-05T01:27:10Z nyef: Or those NOTE-FULL-CALL-SITE things, or whatever they're called.
2016-09-05T01:27:19Z stassats: i'm circling it
2016-09-05T01:27:37Z nyef: Which are supposed to be used for better disassembly annotations or better source-location stuff in the debugger or something like that.
2016-09-05T01:28:02Z nyef: ... Or for the trace-table for gengc.
2016-09-05T01:28:04Z stassats: with https://www.youtube.com/watch?v=ZvCI-gNK_y4 playing
2016-09-05T01:28:20Z stassats: i removed the trace-table
2016-09-05T01:29:36Z stassats: mips ppc and sparc do (setf *assem-scheduler-p* t)
2016-09-05T01:30:05Z stassats: false alarm on ppc, under #+nil
2016-09-05T01:30:39Z stassats: so, branch delays?
2016-09-05T01:30:39Z nyef: Right, the scheduler is supposed to do things like try to put useful stuff in branch delay slots, move things around so that the CPU pipelines don't stall as much while waiting for data, and the like.
2016-09-05T01:30:51Z stassats: or :delay doesn't actually mean branch delay?
2016-09-05T01:31:11Z nyef: It's been a LONG time since I've tried to figure out that part of the assembler.
2016-09-05T01:31:20Z stassats: ok, so, not really dead code
2016-09-05T01:31:28Z stassats: too bad, i wanted to remove something
2016-09-05T01:32:45Z stassats: ok, postits are not used
2016-09-05T01:32:48Z stassats: get 'em
2016-09-05T01:33:11Z nyef: They really aren't used?
2016-09-05T01:33:18Z Guest29115: I think froydnj might have ripped out delay slots
2016-09-05T01:33:31Z stassats: nyef: they are only read, never set to anything
2016-09-05T01:33:35Z nyef: Ah.
2016-09-05T01:33:40Z Guest29115: they're easy to get wrong and marginal on actually fast modern uarch
2016-09-05T01:33:43Z stassats: besides NIL
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2016-09-05T01:35:00Z stassats: so, without postits a simple instruction goes from 402 bytes to 271 bytes
2016-09-05T01:37:49Z stassats: ok, i missed that note-next-instruction calls emit-postit
2016-09-05T01:40:44Z stassats: but that seems unused too
2016-09-05T01:41:20Z nyef: How are fixups tracked?
2016-09-05T01:41:59Z nyef: Ah, I see. Separate mechanism.
2016-09-05T01:44:26Z stassats: handler-bind calls float-fwait on x86
2016-09-05T01:44:39Z stassats: ok, but handler-case expands into %handler-bind, forgoing that wait
2016-09-05T01:45:25Z stassats: i don't understand
2016-09-05T01:47:16Z stassats: ok, i want to rip off the scheduler completely then
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2016-09-05T01:49:55Z stassats: but i want to see if it actually does something on mips
2016-09-05T01:51:09Z nyef: Most modern mips are superscalar anyway, aren't they?
2016-09-05T01:51:32Z stassats: "modern mips" ha-ha
2016-09-05T01:51:44Z nyef: By which I mean "MIPS IV and later".
2016-09-05T01:51:55Z nyef: But there ARE modern MIPS chips.
2016-09-05T01:52:14Z stassats: but they keep using old and slow stuff without fpus
2016-09-05T01:52:22Z stassats: well, if it works it works
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2016-09-05T01:52:38Z nyef: Running test suite on alpha, btw.
2016-09-05T01:53:09Z stassats: might we want this scheduler stuff in the future?
2016-09-05T01:53:18Z nyef: I have no idea.
2016-09-05T01:53:46Z stassats: well, it's cpu dependent, save for stuff with delay slots
2016-09-05T01:53:55Z stassats: so, i guess not in the current form
2016-09-05T02:04:17Z nyef: It's basically a very specific form of peephole optimizer.
2016-09-05T02:16:17Z stassats: ok, sb-dyncount?
2016-09-05T02:17:19Z nyef: Never heard of it being used.
2016-09-05T02:17:41Z stassats: i'm afraid to be removing that many stuff, i'll lay it off
2016-09-05T02:17:44Z nyef: Supposedly something to do with VOP use statistics or something?
2016-09-05T02:18:04Z stassats: the :cost parameter for instructions somehow figures there
2016-09-05T02:18:50Z stassats: i'll just make define-instruction not pollute the emitters with scheduling stuff when it's not needed
2016-09-05T02:25:15Z stassats: wait a moment, it's actually not used on mips
2016-09-05T02:25:29Z stassats: it has (setf *assem-scheduler-p* t), but it affects the expansion of define-instruction
2016-09-05T02:25:36Z stassats: and without an eval-when, it's useless
2016-09-05T02:26:02Z stassats: this is not even funny anymore
2016-09-05T02:26:47Z stassats: so, only sparc
2016-09-05T02:26:57Z stassats: this is pushing me closer to actually nuking it
2016-09-05T02:27:24Z nyef: I'm having enough trouble with sparc right now, can you please leave it until Thursday or so? (-:
2016-09-05T02:27:54Z stassats: ok
2016-09-05T02:28:47Z stassats: i'm a bit fed up with it anyway
2016-09-05T02:28:48Z nyef: Thank you.
2016-09-05T02:30:19Z stassats: maybe till the next release, we had enough upheaval as it is
2016-09-05T02:31:29Z stassats: so, not having postits or hooks (ought to be moved upward) saves 128K
2016-09-05T02:31:39Z stassats: with the scheduler guts removed, should be even more
2016-09-05T02:32:53Z stassats: "needs a little more work in the assembler, to realise that the delays requested here are not mandatory, so that the assembler shouldn't fill gaps with NOPs but with real instructions.  -- CSR,2003-09-08"
2016-09-05T02:33:09Z stassats: i have no doubt that nothing actually has moved in that regard
2016-09-05T02:38:29Z nyef: Seven unexpected failures in the test suite on alpha.
2016-09-05T02:38:39Z nyef: That's... pretty good, under the circumstances.
2016-09-05T02:39:43Z stassats: when am i going to start a compiler without all this cruft?
2016-09-05T02:51:19Z nyef: I've occasionally thought about starting my own compiler, but I still don't have a plan that seems worth the effort.
2016-09-05T02:52:01Z stassats: i'm scheduling right after i make my cpu
2016-09-05T02:54:04Z nyef: Okay, no more programming for me tonight.
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2016-09-05T03:13:46Z loke: nyef: Why not?
2016-09-05T03:16:57Z nyef: Because I've already done quite a bit of debugging, the compile cycles are taking more than an hour, it's already gone eleven PM, and there's stuff to do tomorrow morning.
2016-09-05T03:25:39Z nyef: On the upside, there's basically only one platform left that doesn't have read-only-tramps.
2016-09-05T03:52:03Z loke: nyef: What's a read-only tramt?
2016-09-05T03:52:43Z nyef: We've been moving undefined_tramp, closure_tramp, and funcallable_instance_tramp from arch-assem.S to read-only space.
2016-09-05T03:52:51Z loke: By the way, an SBCL question: Should I expect a "FAILED AVER" error when I have a race condition in plan Lisp code?
2016-09-05T03:53:49Z loke: I acceidentally did that in some CLIM code, and got a FAILED AVER. Then I fixed the race condition and the problem went away. I'd expect all sorts of errors when I have races, but not an internal SBCL crash?
2016-09-05T03:53:52Z nyef: Probably depends on the race condition. Which AVER failed?
2016-09-05T03:54:06Z loke: Don't know. I'll have to try to reproduce.
2016-09-05T03:54:23Z loke: What is an AVER by the way?
2016-09-05T03:54:40Z nyef: It's like an ASSERT, only more forceful.
2016-09-05T03:54:44Z loke: I see.
2016-09-05T03:54:54Z loke: I'll let you guys know when/if I see it again.
2016-09-05T03:55:06Z loke: I'll try to reproduce it.
2016-09-05T03:55:09Z nyef: Crossword puzzle authors seem to confuse AVER and AVOW an awful lot.
2016-09-05T03:55:25Z loke: is "aver" a word?
2016-09-05T03:55:33Z nyef: Yes, it is.
2016-09-05T03:55:38Z loke: I thought it was some internal SBCL acronym :-)
2016-09-05T03:56:21Z loke: Ah, checked the Swedish translations. Now it makes more sense. :-)
2016-09-05T03:56:44Z loke: Kind of "firmly assure" or something like that?
2016-09-05T03:56:56Z nyef: Something like that, yes.
2016-09-05T03:58:40Z nyef: Anyway, read-only-tramps makes it a lot easier to change the encodings for error traps, removes a maintenance hassle from both ALPHA and HPPA backends, and is a lead-in to being able to have a backend without arch-assem.S, which itself has benefits at least for the PPC and x86oid backends.
2016-09-05T04:00:13Z nyef: (Essentially, if we don't have arch-assem.S, we're far less beholden to a particular assembler syntax, so we can change our toolchain a bit. MSVC on x86oids, for example.)
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2016-09-05T04:05:13Z loke: nyef: Don't you already have an assembler as part of the compiler? I mean, I've seen the assembler instructions in the Lisp code?
2016-09-05T04:05:42Z nyef: Exactly!
2016-09-05T04:06:21Z nyef: But some of the assembly code is part of the "runtime", which uses the C compiler's assembler.
2016-09-05T04:06:44Z loke: Oh, I see.
2016-09-05T04:08:21Z nyef: For various reasons, both the ALPHA and HPPA backends manage to have the lisp heap in a separate address space from the C runtime, so that's also a hassle.
2016-09-05T04:08:27Z loke: By the way, is stassats the maintainer of string-case?
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2016-09-05T04:21:28Z 
2016-09-05T04:21:28Z names: ccl-logbot shka_ em1l rszeno oleo_ jrm ASau PuercoPop edgar-rft karswell irsol scymtym Bike whiteline joshe Guest67555 slyrus xristos dougk_ myrkraverk schjetne_ Quadrescence luis jackc-_ abruanese fiddlerwoaroof jdz mood Shinmera dustinm`_ DGASAU White_Flame jzp p_l DeadTrickster eschatologist pootler_ mason salva Posterdati angular_mike carvite minion nzambe foom trinque solene mgodshall Blkt fe[nl]ix chris2 les WojciechK flip214 iskander |3b|
2016-09-05T04:21:28Z names: leo_song payphone jibanes Cthulhux christoph_debian nyef _iwc abbe loke sigjuice drmeister jsnell_ specbot gko jackdaniel brucem nicdev antoszka ferada mordocai pchrist
2016-09-05T04:46:57Z loke: Oh, hello Guest67555
2016-09-05T04:47:12Z loke: There is a performance regression in string-case.
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2016-09-05T07:26:03Z scymtym: minion: memo for stassats: the fixnum-float optimizations seem to have broken something on x86: https://ci.cor-lab.org/job/sbcl-master/1732/featureset=1,label=ubuntu_trusty_32bit/consoleFull (search for "DISASSEMBLY1")
2016-09-05T07:26:03Z minion: Remembered. I'll tell stassats when he/she/it next speaks.
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2016-09-05T08:01:21Z ktt9: Hello! Who governs ~/.cache/common-lisp/sbcl-* directories? Is it a Linux Common Lisp convention, something set by system-wide .rc-file, or an asdf deed?
2016-09-05T08:02:29Z scymtym: it's ASDF's default FASL cache directory for SBCL (on Linux)
2016-09-05T08:21:28Z ktt9: scymtym: thanks.
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2016-09-05T12:54:12Z stassats: FSTPD FR#<DISASSEM-STATE +10 in #<SB-DISASSEM:SEGMENT #X10281073..102810D2[95] in #<code object [1] (LAMBDA (X)) {1028101F}>>>
2016-09-05T12:54:13Z minion: stassats, memo from scymtym: the fixnum-float optimizations seem to have broken something on x86: https://ci.cor-lab.org/job/sbcl-master/1732/featureset=1,label=ubuntu_trusty_32bit/consoleFull (search for "DISASSEMBLY1")
2016-09-05T12:54:15Z stassats: interesting disassembly
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2016-09-05T13:09:12Z stassats: i don't understand the  float-contagion-arg2 transform, why is it about single floats?
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2016-09-05T13:30:12Z nyef: How bad is it to have random garbage with an other-immediate lowtag in a register?
2016-09-05T13:32:37Z nyef: ... And why on earth is scavenge_interrupt_context() scavenging each boxed register twice?
2016-09-05T13:36:52Z nyef: ... what the...?
2016-09-05T13:37:30Z stassats: i think we've already wondered that
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2016-09-05T13:38:28Z nyef: This is one of those "just the wrong header value in a boxed register at the wrong time could cause a gc assertion failure" things.
2016-09-05T13:38:51Z nyef: And I could have sworn that it didn't at one point.
2016-09-05T13:38:53Z stassats: scymtym: fixed the thing, it used 1- instead of -
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2016-09-05T13:53:29Z scymtym: stassats: thanks. new results will be available in ~ 6 hours
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2016-09-05T15:42:25Z nyef: Damnit, stassats!
2016-09-05T15:43:09Z nyef: Commit a966b04d62f1d5aa8c44d3b7874c5497f65c763e deleted the code that I was thinking of that made arbitrary header values "safe" in boxed registers.
2016-09-05T15:44:02Z stassats: but it was there because of a wrong assumption
2016-09-05T15:45:15Z nyef: No, it's there because we occasionally store header values in boxed registers, and we scavenge them with n_words = 1.
2016-09-05T15:45:52Z nyef: Hrm.
2016-09-05T15:46:21Z nyef: The old version wasn't excellent either, but it's better than the status quo.
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2016-09-05T15:47:26Z stassats: the commit said "Maybe fix some gc problems on ppc/gencgc?"
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2016-09-05T15:50:04Z nyef: Look at the semantics: At this point, we know that it's not a pointer. If n_words == 1, we only take ONE WORD. Otherwise, there's a possible overrun screw that gets caught with the gc_assert at the bottom.
2016-09-05T15:51:27Z nyef: The point is that it makes it non-fatal for arbitrary non-pointer garbage to appear in a boxed register.
2016-09-05T15:51:35Z nyef: And, for the most part, it was silent.
2016-09-05T15:51:36Z stassats: so why is there garbage in descriptor registers?
2016-09-05T15:51:57Z nyef: It's not garbage, it's header words!
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2016-09-05T15:52:09Z nyef: Grab an array header, or something.
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2016-09-05T15:53:36Z stassats: header words in >descriptor registers, why?
2016-09-05T15:53:42Z stassats: s/>//
2016-09-05T15:54:33Z nyef: Hrm.
2016-09-05T15:56:02Z stassats: if it's harmless, then it should go back to the old old version
2016-09-05T15:56:13Z stassats: where it was done only for #ifndef LISP_FEATURE_GENCGC
2016-09-05T15:56:28Z nyef: Actually, let's leave it as-is for now.
2016-09-05T15:56:29Z stassats: and it shouldn't print If you can\nreproduce this warning, send a bug report (see manual page for details
2016-09-05T15:56:37Z stassats: otherwise, it should crash hard
2016-09-05T15:56:53Z nyef: We should probably audit for places where we're sticking arbitrary headers into boxed registers instead.
2016-09-05T15:57:05Z stassats: the one on ppc was caused by improper exit from call_into_c
2016-09-05T15:57:20Z stassats: so it got extended into including all non-x86oids
2016-09-05T15:58:29Z stassats: nyef: does it happen reliably for you? which widetag does it get?
2016-09-05T15:58:42Z stassats: sparc, i assume?
2016-09-05T15:58:55Z nyef: Never happens for me, but I was considering taking direct advantage of it.
2016-09-05T15:59:51Z nyef: So now I have a massive audit project on my hands, plus I need to figure out how to fix the NARGS thing.
2016-09-05T16:00:08Z stassats: which nargs thing?
2016-09-05T16:00:49Z nyef: If the COMPUTE-CODE-FROM-whatever instructions need a temporary, that temporary must not be the same SC as NARGS.
2016-09-05T16:01:24Z nyef: Or we arrange for NARGS lifetime to include function entry, somehow.
2016-09-05T16:01:59Z stassats: can't you wire nargs?
2016-09-05T16:02:17Z nyef: No, too much register pressure.
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2016-09-05T16:02:53Z stassats: how come? sparc has like 32 registers
2016-09-05T16:02:55Z nyef: Okay, yes, a wired TN, but the lifetime needs to be controlled.
2016-09-05T16:04:15Z stassats: that's only a problem for xep-allocate-frame?
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2016-09-05T16:04:48Z nyef: I don't know at this point. I have to refresh my memory on the overall calling convention.
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2016-09-05T16:05:34Z stassats: but why nargs? why not other register args?
2016-09-05T16:07:03Z nyef: The temporary required is (almost?) invariably an unboxed register. NARGS is often an unboxed register. Register args are all boxed.
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2016-09-05T16:08:08Z stassats: and right now it's non-descriptor-reg for the temporary
2016-09-05T16:08:28Z stassats: but didn't you say that compute-code puts a descrptor value into it?
2016-09-05T16:08:38Z nyef: On ARM, yes.
2016-09-05T16:09:09Z nyef: On most other platforms, it's a displacement that happens to have an other-immediate lowtag.
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2016-09-05T16:10:31Z stassats: and where does it get assigned to nargs?
2016-09-05T16:12:29Z nyef: IIRC, ARM NARGS is a boxed register, and the temporary is unboxed. The problem being that the temporary holds a boxed value.
2016-09-05T16:13:07Z nyef: ... And I'm wrong.
2016-09-05T16:13:09Z nyef: Good grief.
2016-09-05T16:13:13Z stassats: nargs is a non-descriptor-reg
2016-09-05T16:13:14Z stassats: on arm
2016-09-05T16:13:52Z stassats: it is a descriptor on alpha
2016-09-05T16:13:56Z nyef: Right, the ARM scenario is the normal one where the temporary can collide NARGS.
2016-09-05T16:14:04Z nyef: Good-news, bad-news.
2016-09-05T16:14:08Z stassats: and alpha only
2016-09-05T16:14:42Z stassats: have you witnessed a collision somewhere?
2016-09-05T16:15:05Z fe[nl]ix: can we please get rid of Alpha support ?
2016-09-05T16:15:06Z nyef: I have a collision where the temporary in XEP-ALLOCATE-FRAME winds up being NARGS. On SPARC.
2016-09-05T16:15:21Z stassats: ok, sparc
2016-09-05T16:15:26Z nyef: fe[nl]ix: Can we please not get rid of it?
2016-09-05T16:16:56Z nyef: Next thing I know, you'll be asking to get rid of HPPA support. d-:
2016-09-05T16:16:57Z stassats: can you wire the temporary yourself then?
2016-09-05T16:16:59Z stassats: to non nargs?
2016-09-05T16:17:25Z nyef: Might have to. Or wire NARGS and figure out how to make it not get killed.
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2016-09-05T16:17:42Z nyef: ... which is suddenly stunningly obvious.
2016-09-05T16:17:49Z fe[nl]ix: nyef: of course. AIX too
2016-09-05T16:17:59Z stassats: hppa does wire it
2016-09-05T16:18:09Z stassats: fe[nl]ix: the AIX port is work in progress
2016-09-05T16:18:56Z nyef: Oh, nice!
2016-09-05T16:19:01Z nyef: Thank gou.
2016-09-05T16:19:05Z nyef: Err... Thank you.
2016-09-05T16:19:26Z stassats: just need to get rid of ppc-assem.S
2016-09-05T16:20:12Z nyef sighs.
2016-09-05T16:20:23Z nyef: Commit 0cb0cd9687074e4da4900d3e03a7a0a122625b43 introduced that KLUDGE on HPPA.
2016-09-05T16:20:30Z nyef: I feel silly now.
2016-09-05T16:21:39Z nyef: So, a simple enough audit and patch job.
2016-09-05T16:22:03Z stassats: feels dirty
2016-09-05T16:22:14Z nyef: Yes, that is what KLUDGE implies.
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2016-09-05T16:22:40Z stassats: can we somehow wire all the necessary registers?
2016-09-05T16:22:55Z stassats: say, code-tn, it doesn't get killed, is it component live or something?
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2016-09-05T16:23:44Z nyef: code isn't in any of the normal SCs.
2016-09-05T16:24:04Z nyef: So the compiler never tries to pack anything in there.
2016-09-05T16:24:27Z nyef: NFP will tend to be component-live at times, IIRC.
2016-09-05T16:25:31Z stassats: ok, copy-more-arg?
2016-09-05T16:25:53Z stassats: seems to be always hard wired
2016-09-05T16:25:57Z nyef: Yeah. Same thing.
2016-09-05T16:26:56Z stassats: i guess there is no point in fighting it
2016-09-05T16:27:18Z nyef: I don't have time to fix this now, but I should later this afternoon or this evening, and failing that I definitely should tomorrow.
2016-09-05T16:27:26Z stassats: easy on arm64, it has a dedicated temp registers
2016-09-05T16:27:43Z stassats: register
2016-09-05T16:28:19Z stassats: (as does x86-64, but no code-tn anyway)
2016-09-05T16:29:19Z stassats: i think compute code on arm should just apply an offset to PC, without any trickery
2016-09-05T16:29:26Z stassats: most of the time can be done in 1 instruction
2016-09-05T16:31:03Z nyef: Feel free. My main concern with the arm port was making it happen.
2016-09-05T16:31:21Z stassats: well, i have no concerns for the arm port anymore
2016-09-05T16:31:42Z stassats: consider it a stepping stone to arm64
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2016-09-05T17:34:50Z madbub: Hey guys, is there anywhere I can get some information on how SBCL internals is organized (besides reading the source code)?
2016-09-05T17:35:18Z stassats: you have to read the source code
2016-09-05T17:35:26Z madbub: I see this bug https://bugs.launchpad.net/sbcl/+bug/1501418, porting SBCL to ppc64el, is open and I'd like to try my hand at it
2016-09-05T17:35:50Z stassats: that's a pretty difficult endeavour
2016-09-05T17:35:58Z stassats: if you don't know anything about SBCL
2016-09-05T17:36:05Z stassats: but after you finish you will know a lot
2016-09-05T17:36:46Z madbub: stassats: yeah, that's what I'm trying to figure out now :P Is there any tip you could give me on how to approach SBCL's code so I can understand how it works?
2016-09-05T17:37:41Z stassats: "how it works?" there is a gazillion of intermingled piece all working together to bring you SBCL
2016-09-05T17:44:15Z madbub: guess I gotta start somewhere. I'll have start going through the code and maybe pop some questions around here when I get stuck
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2016-09-05T20:01:03Z nyef: ... What, not recommending reading the arm-port-log?
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2016-09-05T20:01:47Z stassats: well, i'm not recommending starting with doing a port
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2016-09-05T20:09:38Z nyef: Right, but it's a good tour of the sorts of things you need to know about in order to DO a port.
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2016-09-05T20:15:26Z nyef: Ugh. My sparc takes its own sweet time about starting up. /-:
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2016-09-05T20:26:33Z nyef: Sparc build running. If this one works, maybe I'll manage to get the trampolines sorted out tonight.
2016-09-05T20:33:54Z DougNYC: Which Sparc and operating system nyef?
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2016-09-05T20:34:52Z stassats: obviously not solaris
2016-09-05T20:35:03Z stassats: which is so broken with sbcl
2016-09-05T20:36:44Z nyef: I'm running Linux on a SunFire v210, IIRC.
2016-09-05T20:37:23Z nyef: The server is loud, and it sits in my bedroom, so I don't run it very often. (-:
2016-09-05T20:37:32Z DougNYC: LOL. I was hoping you were going to say Sun 4/110 with SunOS 4.1
2016-09-05T20:37:59Z DougNYC: It takes about a day to compile on a SparcStation 20 (for the old version that it will compile on)
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2016-09-05T21:08:17Z nyef: So, a brutal test idea, for systems that can execute a single instruction at a time: during call-into-lisp, arrange to enable the single-instruction stepping, and disable it during call-into-c. Force a GC at every instruction boundary while the gc is enabled and not blocked by either P-A, WITHOUT-INTERRUPTS, or WITHOUT-GCING.
2016-09-05T21:10:12Z stassats: i did a localized version of this
2016-09-05T21:10:17Z nyef: This, of course, will be slow, but it will also be absolutely ruthless when it comes to GC invariant violations.
2016-09-05T21:10:31Z stassats: to test some i inserted a pending interrupt trap
2016-09-05T21:11:07Z stassats: and setting sb-c::*gc-pending* to T
2016-09-05T21:11:34Z stassats: worked well
2016-09-05T21:11:42Z nyef: That test case that was blowing up on sparc isn't anymore. Progress!
2016-09-05T21:12:11Z nyef: Running the full test suite now.
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2016-09-05T21:36:49Z nyef: Hrm. That's new.
2016-09-05T21:37:05Z nyef: "Kernel panic - not syncing: Irrecoverable deferred error trap."
2016-09-05T21:38:17Z nyef: Hit during stream.impure.lisp.
2016-09-05T21:40:55Z nyef: And, of course, the system is still running.
2016-09-05T21:41:08Z nyef: It just locked up the test process. WTF?
2016-09-05T21:41:18Z nyef: Probably the ALOM console connection timing out or something.
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2016-09-05T22:39:10Z nyef: ... That panic seems to have caused a few issues. Rebooting the sparc. /-:
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2016-09-05T23:26:16Z nyef: Finally, a baseline test run completed.
2016-09-05T23:37:39Z stassats: hacker's delight has something for floating points, got check it out, might be something useful
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